Search results for "MOS current-mode logic"
showing 4 items of 4 documents
Analysis of compressor architectures in MOS current-mode logic
2010
This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS tec…
A Methodology for the Design of MOS Current-Mode Logic Circuits
2010
In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitan…
Power-aware design of MCML logarithmic adders
2010
This paper describes the low-power design of a MOS current-mode logarithmic adder. The adder utilizes the Brent-Kung tree structure. The design strategy adopted is very simple and effective. Moreover, it can be utilized also for other types of logarithmic adders. To validate it, several adders were designed in a TSMC CMOS 130nm technology. Results of simulations indicate that the proposed methodology offers a good starting point before fine-tuning the design by SPICE simulations. Finally, the tradeoff that can be realized between performance and power consumption is discussed.
Energy-Delay Efficiency of MCML Gates
2012
In this paper, the energy-delay tradeoff that can be realized between energy and delay for MCML gates is explored using the energy-efficient curve. Two metric, namely, the energy-delay gain and the delay-energy gain are employed to quantify it. Moreover, a methodology is introduced for the minimization of the energy-delay product. Experiments were performed in 130nm and 45nm technologies.